A recent surge in the use of wearable and Internet of Things (IoT) devices demands a higher level of power efficiency to provide an extended battery run-time. Inspired by the way the brain processes the information, scientists and electrical engineers are coming up with alternate computing paradigms that try to reduce the power required for doing arithmetic computations.
Let’s consider for a while, as to what happens when someone asks you to divide 100 by 10. Your brain tells you that it’s easy and quickly responds back by telling you the result. Compare this to a division of 72 by 7, and your brain is challenged. You will quickly say “approximately 10”, however, your brain shall have to put in more effort to compute the exact answer (10.285). The brain has to think harder and spend more computing power to try to come up with an answer. This is an amazing capability of the human brain. It puts more computing effort to solve “problems that require” more accuracy while lower effort for problems that require less accuracy. This is in essence, the principle for “Approximate Computing” i.e. you spend “minimum computing effort that provides acceptable” results for your particular application.
Approximate Computing, thus, relies on relaxing the bounds of precise computing to provide new opportunities for improving the area, power, and performance efficiency of on-chip systems by orders of magnitude at the cost of reduced output quality. Recent investigations by researchers at organizations like Intel, IBM and Microsoft have shown that there is a large body of resource-hungry applications that can tolerate approximation errors and a significant portion of their functions/computations still produces outputs that are useful and of acceptable quality for users.
Researchers have been able to produce basic arithmetic units such as adders that require less than half of the power as compared to that of a fully accurate adder. The challenge here is to find the right balance of approximation and quality of output. Towards this end, researchers in Pakistan are putting in an effort that they believe will result in tools, analysis and open source libraries that shall help application engineers to quickly evaluate the applicability and extent of use of approximate computing for their particular application. The work is a joint effort by researchers from Vienna University of Technology, KIT Germany, TU Dresden Germany, Information Technology University, Pakistan and the National University of Sciences and Technology, Pakistan.
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The group presented its latest findings at a talk in the 53rd Design Automation Conference (DAC) in Austin-USA, titled “Cross-Layer Approximate Computing: From Logic to Architectures.” DAC is the top conference in the area of computer aided design. The paper introduces the collaborative work that provides a methodology to develop accelerators with variable approximation modes, using multi-bit approximate adders and multipliers. It further provides a foundation for realizing approximate computing architectures for hardware accelerators.
In another published article in the journal IEEE Transactions on Computer, titled, “Probabilistic Error Modeling for Approximate Adders,” a unified methodology for estimating the error incurred due to approximate addition was presented. It was demonstrated that, using the proposed analysis, the comparative performance of different approximate adders can be correctly predicted for a number of applications related to image processing and computer vision. A recent follow up article, “Probabilistic Error Analysis of Approximate Recursive Multipliers,” related to the extension of error analysis to approximate multipliers was also published in IEEE Transactions on Computers. These two works combined, provide the basis for in-depth error analysis for a class of algorithms that involve linear functions.
The research in the area of Approximate Computing is still in its initial stages and a lot of collaborative and open source effort is required by the research community to make it a reality. Once it becomes a reality, it can translate into considerable savings in the power requirement, specifically for signal processing and multimedia applications. Considering the use of such applications in wearable devices, IoT and smartphones,this research can significantly benefit in extending the runtime of these battery powered devices.
Dr. Rehan Hafiz has a PhD in Reconfigurable Signal Processing from the University of Manchester. He has over eight years of R&D experience in the area of Vision System Design, FPGA based design and Immersive multimedia projection. Dr. Hafiz holds multiple US and Korean patents. He is the director of the VISpro Lab and an Associate Professor at Information Technology University, Pakistan. For collaborative research and further information, Dr. Rehan Hafiz can be contacted at: email@example.com.